1. Field of the Invention
The present invention relates to non-volatile semiconductor memory devices employed in various computing devices, control equipment or the like, and a manufacturing method thereof
2. Description of the Background Art
A non-volatile semiconductor memory device is used for writing/reading a piece of information, based on change in electric field effect to a channel portion caused by the electric charge in the floating gate, by applying a high voltage between a floating gate and a source or a drain, and injecting/pulling electric charge into/out from the floating gate. As the electric charge in the floating gate is isolated by an insulation film, it can be retained for a long time as non-volatile information even after the power-off.
A conventional non-volatile semiconductor memory device will be described with reference to FIG. 53.
On a floating gate fin electrode 509, a second gate insulation film 512 is formed and a control gate lower electrode 513 of polycrystalline silicon and a control gate upper electrode 514 of a metal silicide film are formed thereon. A control gate electrode 517 is formed of control gate lower electrode 513 and control gate upper electrode 514. Further on control gate upper electrode 514 of the metal silicide film, a hard mask 515 which selves as a mask at etching is formed of a silicon oxide film.
Bit lines are arranged among sources/drains from the back to the front and word lines. are arranged from the right to the left in the drawing.
In FIG. 53, control gate electrode 517 and second gate insulation film 512 in the front section are not shown to allow the viewer to see a central trench portion. A structure shown in FIG. 53 is formed by etching control gate electrode 517 and second gate insulation film 512 using hard mask 515 of a silicon oxide film as a mask, removing a floating gate layer through anisotropic etching using control gate electrode 517 as a mask, and thereby forming a floating gate electrode 518. Here, a polycrystalline silicon residue which is an etching residue 519 is left on a side wall of an insulation film facing the central trench portion.
Another example where etching residue remains is shown in FIGS. 54 and 55. An end portion itself of a floating gate electrode 618 serves as a mask at a step formed by an end of floating gate electrode 618 and an isolating insulation film 602, and a polycrystalline silicon residue 619 is produced on a side wall of the step formed by isolating insulation film 602 and the end of the floating gate electrode as shown in FIG. 55.
Generally, in a non-volatile semiconductor memory device such as a flash memory, capacitance coupling ratio C2/(C1+C2) must be high. Here, capacitance C1 is capacitance between the floating gate electrode and a channel portion and capacitance C2 is coupling capacitance between the control gate electrode and the floating gate electrode. When voltage V is applied from an external source to the control gate electrode, potential on the floating gate electrode is C2/(C1+C2). Therefore, in order to apply a sufficiently high voltage on the floating gate electrode, a correspondingly high capacitance coupling ratio is required. The high capacitance coupling ratio allows an operation of non-volatile semiconductor memory device at a low voltage while securing a high floating gate potential.
To increase the capacitance coupling ratio, capacitance C2 between the control gate electrode and the floating gate electrode must be increased. Therefore, a fin electrode 509 is provided in an upper portion of the floating gate electrode thereby increasing the area between the floating gate electrode and the control gate electrode.
In the above described structure, some portions are undesirably masked from being etched at the anisotropic etching of floating gate electrode 518 of polycrystalline silicon or the like, and etching residue 519 tends to be produced along the side wall of the insulation film facing the trench portion. Such polycrystalline silicon residue forms short circuits between gate electrodes and as a result causes a significant yield reduction. In addition, even if etching selectivity between polycrystalline silicon and an underlying layer is made as high as possible to permit over-etching for the removal of the etching residue, there is a certain limitation in the etching selectivity and first gate insulation film 503 possibly be penetrated.
In addition, in non-volatile semiconductor memory devices such as a flash memory, for the increase in capacitance C2 between the floating gate electrode and the control gate electrode which in turn increases the above mentioned capacitance coupling ratio, an area of the floating gate electrode, especially width thereof must be increased. Conventionally, the width of the floating gate electrode is increased by providing fin electrode 509 up to about three times the length of the channel portion. Therefore, the area of the floating gate electrodes is increased and hinders the miniaturization of non-volatile semiconductor memory devices.
An object of the present invention is to remove an etching residue or make the etching residue harmless without damaging a first gate insulation film and an interlayer insulation film. A further object of the present invention is to obtain a high capacitance coupling ratio without increasing an area of a floating gate electrode and to attain miniaturization of non-volatile semiconductor memory devices.
In one aspect of the present invention, a method of manufacturing includes the steps of: forming a first gate layer on a main surface of a semiconductor substrate with a first gate insulation film posed therebetween; forming a second gate layer on the first gate layer with a second gate insulation film posed therebetween; forming a second gate electrode by etching the second gate layer using a resist as a mask; forming a first gate electrode by etching the first gate layer using the second gate electrode as a mask; and performing an isotropic etching on an etching residue left on a side wall of a step formed by an insulation film in contact with a side wall of the first gate layer and the first gate insulation film, after the etching of the first gate layer, to remove the etching residue.
As the etching residue is removed by isotropic etching, short circuit between gate electrodes can be prevented and yield improvement can be achieved.
Preferably, a gas containing halogen element is employed in the above mentioned isotropic etching.
The etching residue can be removed without damages on the first gate insulation film and the interlayer insulation film through the use of gas containing halogen element, and yield improvement can be achieved.
In particular, the gas containing halogen element is preferably one of the following gases (1), (2) and (3).
(1) One selected from the group consisting of Cl2 gas, a mixed gas of Cl2 and NF3, a mixed gas of Cl2 and O2, a mixed gas of Vapor HF and O2, a mixed gas of CF4 and O2, a mixed gas of CHF3 and O2, a mixed gas of SF6 and O2, and a mixed gas of NF3 and O2.
(2) A gas prepared by using one of N2O, CO2, O3, H2O2 and H2O instead of O2 in the gas of (1).
(3) A mixed gas prepared by further adding at least one of He, Ne, Ar, Kr, Xe and N2 to the gas of (1).
In addition, a gas prepared by adding at least one of He, Ne, Ar, Kr, Xe and N2 to the gas of (2) can be employed.
With the use of these gases, the etching residue can be efficiently removed without damages on the first gate insulation film and the interlayer insulation film. As a result, short circuit between gates can be prevented and yield improvement is allowed.
When formation of a non-uniformly etched side wall of the second gate electrode is not desired at the above mentioned isotropic etching, a step of forming a protective film on the side wall of the second gate electrode desirably is further included prior to the step of performing the isotropic etching.
By the formation of the protective film, the non-uniformity in etching of the second gate electrode can be prevented especially when it is formed of a metal silicide layer. Therefore, the etching residue causing short circuit between gate electrodes can be removed while variations in dimension and interconnection resistance are suppressed. In addition, with no damages on the first gate insulation film and the interlayer insulation film, yield improvement is allowed.
In accordance with the one aspect of the present invention, in order to prevent the non-uniformity in oxidation of the side surfaces of the gate electrodes caused at the isotropic etching, the manufacturing method desirably further includes a step of performing a wet process on the etching residue with a chemical containing at least 1% of H2O2 prior to the step of performing the isotropic etching, to make uniform the thicknesses of oxide films on the side walls of the gate electrode after the isotropic etching.
By the wet process with the chemical containing at least 1% of H2O2, the thicknesses of the oxide films on the side walls of the first and second gate electrodes become uniform and the removal of etching residue is allowed without causing variations in dimension and interconnection resistance. In addition, with no damages on the first gate insulation film and the interlayer insulation film, yield improvement can be achieved.
In accordance with a further aspect of the present invention, when removal of etching residue by the wet process is important, the method of manufacturing includes the steps of: forming a first gate lower layer on a main surface of a semiconductor substrate with a first gate insulation film posed therebetween; forming sidewall spacers of an insulation film on side walls of the first gate lower layer and an insulation film formed thereon; forming an interlayer insulation film in contact with the sidewall spacer, from an insulation film of a material different from the sidewall spacer; forming a second gate layer on a first gate layer with a second gate insulation film posed therebetween; forming a second gate electrode by etching the second gate layer using a resist as a mask; forming a first gate electrode by etching the first gate layer using the second gate electrode as a mask; and performing a wet process on the sidewall spacer after the formation of the first gate electrode through etching of the first gate layer, removing the sidewall spacer, and removing by lift-off an etching residue left on a side wall of a step formed by the sidewall spacer and the first gate insulation film.
By the wet process involving the lift-off, the etching residue can be securely removed together with the sidewall spacer, whereby short circuit can be prevented from being caused by the etching residue with high reliability. As a result, a significant yield improvement can be achieved.
When the etching residue is lift off by the removal of sidewall spacer as described above, if protection of a side wall of second gate electrode is important, a step of forming a sidewall of an insulation film on the side wall of the second gate electrode is desirably further included after the step of forming the second gate electrode and prior to the step of forming the first gate electrode.
By providing a protective film on the side wall of the second gate electrode as described above, short circuit between gate electrodes as well as the damages on the second gate electrode can be prevented and yield improvement can be achieved.
In accordance with a still further aspect of the present invention, when it is important to taper the central trench portion to make width thereof wider towards the top of the trench at the anisotropic etching for the formation of the first gate electrode, the method of manufacturing includes the steps of: forming a photo resist or an insulation film on a main surface of a semiconductor substrate at a position where a gate electrode is to be formed; forming an active region by implanting an impurity into the semiconductor substrate using the photo resist or the insulation film as a mask; forming an interlayer insulation film on the semiconductor substrate; etching the interlayer insulation film, forming a trench in a position where the gate electrode is to be formed, and tapering opposing sides of the trench to widen the width towards the top of the trench, in a section perpendicular to a direction of extension of the trench; and forming a first gate electrode along the trench.
With the above described tapered trench portion having a wider width towards the top, a portion of the first gate electrode layer to be etched become easily accessible. As a result, the etching residue is not left on the side surface of the trench, and short circuit between gate electrodes is prevented. In addition as no damages are caused in other portions, yield improvement is allowed.
In accordance with a still further aspect of the present invention, when it is important to form a tapered trench wider towards the top by forming a tapered silicon nitride film having an upper surface wider than a bottom surface, the method of manufacturing includes the steps of: depositing a silicon nitride film on a main surface of a semiconductor substrate; selectively etching the silicon nitride film so as to be left in a position where a gate electrode is to be formed with a resist as a mask and tapering each of opposing sides of the silicon nitride film so as to widen the width of the silicon nitride film upwards, in the section perpendicular to extension of the side wall of the silicon nitride film; forming an active region by implanting an impurity into the semiconductor substrate using the silicon nitride film as a mask; forming an interlayer insulation film on the semiconductor substrate; removing the silicon nitride film, forming a trench with each of opposing sides of the trench being tapered in the section to widen the width of the trench upwards; and forming a first gate electrode along the trench.
When the first gate electrode is formed along the tapered trench with widened width towards the top, no portion is blocked from etching. As a result, no etching residue is produced and short circuit is not generated whereby yield improvement is allowed.
In accordance with the one aspect of the present invention, when prevention of short circuit between gate electrodes is important along with the protection of the side wall of the second gate region, a non-volatile semiconductor memory device includes: a first gate insulation film formed on a main surface of a semiconductor substrate; a first gate electrode formed thereon; a second gate electrode formed on the first gate electrode with a second gate insulation film posed therebetween; and a protective film on a side wall of the second gate electrode.
By providing a protective film on the side wall of the second gate electrode, side etching does not occur on the side wall of the second gate electrode at the formation of the first gate electrode through the etching of the first gate layer. As a result, a non-volatile semiconductor memory device preventing short circuit between gate electrodes without causing variations in dimension of the side wall of the second gate electrode and the interconnection resistance can be provided.
In accordance with the further aspect of the present invention, a non-volatile semiconductor memory device includes; a first gate insulation film formed on a main surface of a semiconductor substrate; a first gate electrode formed thereon; a second gate electrode formed on the first gate electrode with a second gate insulation film posed therebetween; and silicon compound formed by turning a polycrystalline silicon into an insulation on a step side wall formed by an insulation film in contact with a side wall of the first gate electrode and the first gate insulation film.
By turning the etching residue formed on the step side wall into an insulation, short circuit between gate electrodes can be prevented from being caused by the etching residue. As a result, yield improvement and an inexpensive device can be provided. Here, thermal oxidation, nitriding or ion implantation can be employed as a process for turning the etching residue into an insulation.
In accordance with the still further aspect of the present invention, when it is important not to produce etching residue from the time of anisotropic etching, a non-volatile semiconductor memory device includes: a first gate electrode formed by etching a first gate layer on a semiconductor substrate with a first gate insulation film posed therebetween; and a second gate electrode formed by etching a second gate layer on the first gate electrode with a second gate insulation film posed therebetween; an angle formed by an insulation film in contact with a side wall of the first gate electrode and the first gate insulation film being more than 90xc2x0 with respect to the first gate electrode in a section perpendicular to extension of the side wall of the first gate electrode, and each of opposing side walls of the insulation film in contact with the side wall of the first gate electrode being tapered so as to widen the width of the first gate electrode upwards.
By setting the angle formed by the insulation film in contact with the side wall of the first gate electrode and the first gate insulation film larger than 90xc2x0 with respect to the first gate electrode in a section perpendicular to the extension of the side wall of the first gate electrode, no portion is blocked from the etching at the anisotropic etching for forming the first gate electrode. As a result, etching residue is not produced and short circuit between gate electrodes can be prevented.
In accordance with the still further aspect of the present invention, when it is important that the device is miniaturized, a non-volatile semiconductor memory device includes: a first gate lower electrode formed on a main surface of a semiconductor substrate with a first gate insulation film posed therebetween; a first interlayer insulation film thicker than the first gate lower electrode and defining width of the first gate lower electrode; a second interlayer insulation film formed on the first interlayer insulation film; a first gate fin electrode formed on the first gate lower electrode, having a fin portion extending in the periphery of the first interlayer insulation film and along a side wall of the second interlayer insulation film, and making up a first gate electrode together with the first gate lower electrode; and a second gate electrode formed on the first gate fin electrode with a second gate insulation film posed therebetween.
As described above, by forming the fin portion as the first gate fin electrode extending in the periphery of the first interlayer insulation film and along the side wall of the second interlayer insulation film, a substantial area between the first gate electrode and the second gate electrode can be increased without increase in the plane area. As a result, a miniaturized non-volatile semiconductor memory device having a high coupling capacitance ratio can be provided at an inexpensive cost, and an operation at a low voltage of the device is allowed.
In addition, in the non-volatile semiconductor memory device in accordance with the further aspect of the present invention, a protective film is desirably provided on a side wall of the second gate electrode.
By providing the protective film on the side wall of the second gate electrode, even in the non-volatile semiconductor memory device described above having the fin portion along the side wall of the second interlayer insulation film, etching residue can be removed by isotropic etching without damaging the second gate electrode.
In addition, in accordance with the still further aspect of the present invention, the non-volatile semiconductor memory device further includes silicon compound formed by turning polycrystalline silicon into an insulation on a side wall of one of a step formed by an insulation film in contact with a side wall of the first gate lower electrode and the first gate insulation film, and a step formed by the first interlayer insulation film and the second interlayer insulation film.
By providing a compound formed by turning the etching residue into an insulation on the side wall of the above mentioned step, short circuit between gate electrodes can be prevented. When thermal oxidation, nitriding, or ion implantation is performed to turn the residue into an insulation, the second gate electrode may be damaged. Therefore, a protective film is desirably formed on the side wall of the second gate electrode in the non-volatile semiconductor memory device having a silicon compound as an insulation.
In the non-volatile semiconductor memory device achieving a high capacitance coupling ratio as described above, desirably an angle formed by the side wall of the insulation film in contact with the side wall of the first gate lower electrode and the first gate insulation film is more than 90xc2x0 with respect to the first gate lower electrode in a section perpendicular to extension of the first gate lower electrode, and each of opposing side walls of the insulation film in contact with opposing side walls of the first gate lower electrode is tapered so as to widen the width of the first gate lower electrode upwards.
As described above, by tapering the side wall of the insulation film such that the opening formed by the first gate lower electrode becomes wider towards the top, no portion is blocked from etching, whereby etching residue is not produced.
In the non-volatile semiconductor memory device achieving a high capacitance coupling ratio as described above, further desirably, an angle formed by an upper surface of the first interlayer insulation film and the side wall of the second interlayer insulation film is more than 90xc2x0 with respect to the upper surface of the first interlayer insulation film in contact with the fin portion, and each of opposing side walls of the second interlayer insulation film is tapered so as to widen the widths of the first gate fin electrode and the second gate electrode upwards.
By providing the tapered side wall of the second interlayer insulation film such that the widths of the first gate fin electrode and the second gate electrode become wider towards the top, also at the step formed by the upper surface of the first interlayer insulation film and the second interlayer insulation film, no portion is blocked from etching. As a result, the tapered side wall of the second interlayer insulation film as well as the tapered side wall of the insulation film at the step formed by the insulation film in contact with the side wall of the first gate lower electrode and the first gate insulation film, allow the removal of etching residue at both step portion, and even more secure prevention of short circuit between gate electrodes is allowed.
In the non-volatile semiconductor memory device achieving a high capacitance coupling ratio as described above, when decreases in area and cost are important, at least a surface of the fin portion in the first gate fin electrode is desirably roughened. The roughening treatment is also desirable when (a) silicon compound turned into an insulation is included, (b) the first gate lower electrode is tapered such that it becomes wider towards the top, or (c) in addition to the first gate lower electrode, the second gate electrode is also tapered such that it becomes wider towards the top.
By roughening at least the surface of the fin portion in the non-volatile semiconductor memory device, a substantial area between the first gate electrode and the second gate electrode is increased. As a result, a miniaturized and inexpensive non-volatile semiconductor memory device having a high coupling capacitance ratio can be provided. In addition, an operation at a still lower voltage is allowed for the above described device.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.